ISBN-10:
1441964770
ISBN-13:
9781441964779
Pub. Date:
09/27/2010
Publisher:
Springer New York
Extreme Low-Power Mixed Signal IC Design: Subthreshold Source-Coupled Circuits / Edition 1

Extreme Low-Power Mixed Signal IC Design: Subthreshold Source-Coupled Circuits / Edition 1

by Armin Tajalli, Yusuf Leblebici

Hardcover

Current price is , Original price is $179.99. You
Select a Purchase Option (2010)
  • purchase options
    $121.33 $179.99 Save 33% Current price is $121.33, Original price is $179.99. You Save 33%.
  • purchase options

Overview

Extreme Low-Power Mixed Signal IC Design: Subthreshold Source-Coupled Circuits / Edition 1

This book describes a completely novel class of techniques for designing ultra-low-power integrated circuits (ICs). In many applications such as battery operated systems and battery-less (energy-scavenging) systems, power dissipation is a critical parameter. As a result, there is a growing demand for reducing the power (energy) consumption in ICs to extremely low levels, not achievable by using classical "subthreshold CMOS" techniques. This book introduces a new family of "subthreshold circuits" called "source-coupled circuits". This family of circuits can be used for implementing digital (logic) circuits that dissipate far less than 1fJ per switching event, yet maintain the noise margins that are necessary for robust operation. This book also explains how the techniques used for implementing ultra low-power digital circuits could be extended for implementing analog circuits. Developing a uniform basis for designing ultra-low-power digital and analog circuits provides the basis for realizing complicated mixed-signal integrated systems.

Product Details

ISBN-13: 9781441964779
Publisher: Springer New York
Publication date: 09/27/2010
Edition description: 2010
Pages: 274
Product dimensions: 5.98(w) x 9.02(h) x 0.03(d)

Table of Contents

1 Introduction 1

1.1 Applications of Widely Adjustable Circuits and Systems 2

1.1.1 Performance Scalability and Requirements 5

1.2 Prior Art 6

1.2.1 Digital Circuits 6

1.2.2 Analog Circuits 8

1.3 Organization 10

References 11

2 Subthreshold MOS for Ultra-Low Power 15

2.1 MOS Technology 15

2.2 Device Modeling 16

2.2.1 I-V Characteristics 16

2.2.2 Second Order Effects 19

2.3 Design Considerations in Subthreshold 21

2.3.1 PVT Variation 21

2.3.2 Matching 23

2.3.3 Noise 26

2.4 Ultra-Low-Power Design Using Subthreshold MOS 29

2.4.1 MOS Transistor Leakage Mechanisms 30

2.4.2 Leakage Reduction Techniques 36

2.5 Impacts of Variation on Subthreshold CMOS Operation 37

2.5.1 Noise Margin 39

2.5.2 Energy Consumption 45

2.5.3 Optimal Design with Technology Scaling 49

2.5.4 Supply Voltage and Threshold Voltage Scaling for Optimal Design 53

References 56

Part I Scalable and Ultra-Low-Power Digital Integrated Circuits

3 Subthreshold Source-Coupled Logic 61

3.1 Introduction 61

3.2 Conventional SCL Topology 63

3.2.1 Circuit Topology 63

3.2.2 Tradeoffs in Design of Strong-Inversion SCL Gates 67

3.3 Ultra-Low-Power Source-Coupled Logic 70

3.3.1 High-Valued Load Device Concept 70

3.3.2 STSCL Gates 74

3.4 Design Issues and Performance Estimation 76

3.4.1 Power-Speed Tradeoffs in STSCL 76

3.4.2 Noise Margin 79

3.4.3 Replica Bias Circuit 83

3.4.4 Minimum Operating Current 84

3.4.5 Global Process and Temperature Variation 86

3.4.6 Effect of Mismatch on Delay 87

3.4.7 Minimum Supply Voltage 89

3.5 Experimental Results 89

3.5.1 Basic Building Blocks 89

3.5.2 Ring Oscillator and Frequency Divider 90

3.5.3 Multiplier Circuit 94

3.6 Conclusion 95

References 96

4 STSCL Standard Cell Library Development 99

4.1 Introduction 99

4.2 Standard Cell Library 100

4.2.1 Background 100

4.2.2 Cell Types 101

4.2.3 Cell Layout 101

4.2.4 Characterization 103

4.2.5 LEF File 104

4.2.6 Template Generation 104

4.3 Design Strategies 105

4.3.1 Series-Parallel Tail Bias Transistors 106

4.3.2 Constant Area Scaling 107

4.4 Demonstration Circuits 108

4.4.1 FIR Filter Topology 108

4.4.2 Sample FIR Filter Demonstrator Circuit 109

4.5 Conclusion 112

References 113

5 Subthreshold Source-Coupled Logic Performance Analysis 115

5.1 Introduction 115

5.2 Comparison with the CMOS Topology 116

5.2.1 Ultra-Low-Power Requirements 116

5.2.2 Power-Speed Tradeoff in STSCL 117

5.2.3 Performance Analysis of CMOS Logic Circuits 118

5.2.4 Performance Comparison 121

5.3 Performance Improvement Techniques 122

5.3.1 Compound Logic Style 123

5.3.2 Using Source-Follower Buffer 125

5.3.3 Pipelining Technique 130

5.4 Experimental Results 133

5.4.1 STSCL with Source-Follower Buffer 133

5.4.2 Pipelined Adder Chain 134

5.4.3 Pipelined Multiplier 135

5.5 Conclusions 137

References 138

6 Low-Activity-Rate and Memory Circuits in STSCL 141

6.1 Introduction 141

6.2 Power Efficiency in Low Activity Rates 142

6.2.1 STSCL Topology Performance 142

6.2.2 CMOS Topology Performance 144

6.2.3 Comparison 145

6.3 Low-Leakage CMOS SRAMs 146

6.4 Low Stand-By Current STSCL Memory Cell 149

6.4.1 Circuit Topology 149

6.4.2 Device Sizing 151

6.4.3 Sense Amplifier 152

6.4.4 Leakage Current Detection 153

6.5 Experimental Results 153

6.6 Observations and Discussion 156

References 157

Part II Scalable and Ultra-Low-Power Analog Integrated Circuits

7 Widely Adjustable Continuous-Time Filter Design 161

7.1 Introduction 161

7.2 Amplifier Design 162

7.2.1 Low Power Folded-Cascode Amplifier 162

7.2.2 Widely Adjustable Two-Stage Amplifier 164

7.3 Transconductor-C Filter Design 166

7.3.1 Proposed Biquadratic Filter Topology 166

7.3.2 Dynamic Range 170

7.3.3 Sixth Order gm-C Filter 171

7.4 MOSFET-C Filter Design 171

7.4.1 Circuit Topology 172

7.4.2 High-Valued Pseudo-Resistance 172

7.4.3 Dynamic Range 175

7.4.4 Second Order MOSFET-C Filter 177

7.5 Experimental Results 178

7.5.1 MOSFET-C Filter 178

7.5.2 gm-C Filter 180

7.5.3 Figure of Merit 182

7.6 Conclusion 183

References 184

8 Scalable Folding and Interpolating ADC Design 187

8.1 Introduction 187

8.2 Previous Art 187

8.3 Folding and Interpolating Analog-to-Digital Converter 189

8.3.1 Basics 189

8.3.2 Building Blocks and Design Tradeoffs 192

8.4 Design of FAI ADC 198

8.4.1 Circuit Topology 199

8.4.2 Ultra Low Power Resistor Ladder 202

8.4.3 Comparator Circuit 204

8.4.4 Encoder 206

8.5 Simulation and Experimental Results 209

8.5.1 Encoder 209

8.5.2 FAI ADC Performance 210

8.6 Conclusion 211

References 212

9 Widely Adjustable Ring Oscillator Based ∑ Δ ADC 215

9.1 Introduction 215

9.2 Background 215

9.2.1 Dynamic Range 215

9.2.2 Improving the Resolution 217

9.3 Performance Scalability in Ring Oscillator Based Δ ∑ ADCs 218

9.3.1 Frequency Domain Adjustability 218

9.3.2 Dynamic Range Adjustment 222

9.4 Top Level Design 223

9.4.1 Sources of Non-Ideality 223

9.4.2 Performance Analysis 226

9.5 Circuit Design 228

9.5.1 Ring Oscillator 228

9.5.2 Logic Circuit 231

9.5.3 Current-Mode Integrator 231

9.6 High Order Modulator Design 233

9.6.1 Analysis and Modeling 233

9.6.2 Behavioral Modeling 237

9.7 Simulations and Experimental Results 240

9.8 Conclusion and Discussion 241

References 242

10 Wide Tuning Range PLL 243

10.1 Introduction 243

10.2 Wide Tuning Range PLLs 243

10.2.1 Background 244

10.2.2 Wide Tuning Range CPLL 246

10.2.3 Design Issues with Wide Tune PLLs 249

10.3 Circuit Design 250

10.3.1 Proposed PLL Topology 250

10.3.2 Ring Oscillator 252

10.3.3 Frequency Divider and Phase-Frequency Detector (PFD) 253

10.3.4 Transconductor 254

10.4 Simulation and Experimental Results 254

10.5 Conclusions 258

References 258

11 Conclusions 261

11.1 Main Contributions 262

11.2 Perspectives 264

References 265

Index 267

Customer Reviews

Most Helpful Customer Reviews

See All Customer Reviews