Flip-Flop Design in Nanometer CMOS: From High Speed to Low Energy

Flip-Flop Design in Nanometer CMOS: From High Speed to Low Energy

Paperback(Softcover reprint of the original 1st ed. 2015)

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Product Details

ISBN-13: 9783319345925
Publisher: Springer International Publishing
Publication date: 08/23/2016
Edition description: Softcover reprint of the original 1st ed. 2015
Pages: 260
Product dimensions: 6.10(w) x 9.25(h) x 0.02(d)

Table of Contents

The Logical Effort Method.- Design in the Energy-Delay Space.- Clocked Storage Elements.- Flip-Flop Optimized Design.- Analysis and Comparison in the Energy-Delay-Area Domain.- Energy Efficiency Versus Clock Slope.- Hold Time Issues and Impact of variations on Flip-Flop Topologies.- Ultra-Fast and Energy-Efficient Pulsed Latch Topologies.

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