Hierarchical Modeling for VLSI Circuit Testing

Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing problem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of ...