Low-Voltage CMOS Log Companding Analog Design

Low—Voltage CMOS Log Companding Analog Design presents in detail state—of—the—art analog circuit techniques for the very low—voltage and low—power design of systems—on—chip in CMOS technologies. The proposed strategy is mainly based on two bases: the Instantaneous Log Companding Theory, and the MOSFET operating in the subthreshold region. The former allows inner compression of the voltage dynamic—range for very low—voltage operation, while the latter is compatible with CMOS technologies and...