MCMs today consist of complex and dense VLSI devices mounted into packages that allow little physical access to internal nodes. The complexity and cost associated with their test and diagnosis are major obstacles to their use. Multi-Chip Module Test Strategies presents state-of-the-art test strategies for MCMs. This volume of original research is designed for engineers interested in practical implementations of MCM test solutions and for designers looking for leading edge test and design-for-testability solutions for their next designs.
Multi-Chip Module Test Strategies consists of eight contributions by leading researchers. It is designed to provide a comprehensive and well-balanced coverage of the MCM test domain.
Multi-Chip Module Test Strategies has also been published as a special issue of the Journal of Electronic Testing: Theory and Applications (JETTA, Volume 10, Numbers 1 and 2).
Table of Contents
Foreword; V.D. Agrawal. MCM Testing Background: Fundamentals of MCM Testing and Design-For-Testability; Y. Zorian. Die Level Testing: Known Good Die; L. Gilg. Substrate Testing: A Survey of Test Techniques for MCM Substrates; M. Swaminathan, et al. Smart Substrate MCMs; A. Gattiker, W. Maly. Electron Beam Probing - A Solution for MCM Test and Failure Analysis; R. Schmid, et al. Module Level Test: MCM Test Strategy Synthesis from Chip Test and Board Test Approaches; A. Flint. Designing 'Dual Personality' IEEE 1149.1 Compliant Multi-Chip Modules; N. Jarwala. An Effective Multi-Chip BIST Scheme; Y. Zorian, H. Bederr. MCM Test Applications: Design-For-Test in a Multiple Substrate Multichip Module; J.A. Jorgenson, R.J. Wagner. A Test Methodology for High Performance MCMs; T.M. Storey, B. McWilliam. Module Level Diagnosis: A Formalization of the IEEE 1149.1-1990 Diagnostic Methodology as Applied to Multichip Modules; K. Posse. Multichip Module Diagnosis by Product-Code Signatures; P. Nagvajara, et al. Simulation Techniques for MCMs: Simulation Techniques for the Manufacturing Test of MCMs; M. Tegethoff, T. Chen. MCM Test Economics: Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die; C.F. Murphy, et al. Index.