Reconfigurable Computing Systems Engineering: Virtualization of Computing Architecture

Reconfigurable Computing Systems Engineering: Virtualization of Computing Architecture

by Lev Kirischian

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Product Details

ISBN-13: 9781439856215
Publisher: Taylor & Francis
Publication date: 05/24/2016
Pages: 346
Product dimensions: 6.40(w) x 9.30(h) x 1.00(d)

About the Author

Lev Kirischian, Ph.D, P.Eng, Member IEEE, has been affiliated with Ryerson University, Canada for 18 years. His research involves dynamically reconfigurable computing systems, automated architectural synthesis of data-stream processors, and workload-adaptive and self-healing reconfigurable architectures. He participated in the research and development of the first-generation Soviet supercomputers with reconfigurable architectures in the 1980s, FPGA-based segment of COFDM modulation technology for digital audio/video broadcasting systems for satellite and terrestrial networks (used in the SiriusXM satellite radio network), workload adaptive and self-restorable space-borne embedded computer platforms, and 3D-panoramic machine vision systems, among other technologies. In the last decade, he has developed and taught several courses associated with high-performance and reconfigurable computing as well as high-level synthesis of application-specific processors.

Table of Contents

Introduction to Reconfigurable Computing Systems
Introduction
Computational Process and Classification of Computing Architectures
Formal Definition of Computing Architecture
Correspondence between the Task and the Computing Architecture
Concept of a Computing System with a Programmable Procedure
Concept of an Application-Specific Computing System
Concept of the Computing System with Programmable Architecture
Organization of RCS and Major Components of the RCS Architecture
Summary
Exercises and Problems
References

Organization of the Field of Configurable Resources
Introduction
Granularity of Logic Elements for the FCR
Heterogeneous Organization of the FCR
Dynamic versus Static Reconfiguration of Resources in FCR
Spatial versus Temporal Partitioning of Resources in an FCR
Summary
Exercises and Problems
References

Architecture of the On-Chip Processing Elements
Introduction
Architecture of the Fine-Grained Configurable Processing Elements
Architecture of the Coarse-Grained Configurable Processing Elements
Architecture of the Hybrid Programmable Processing Elements
Summary
Exercises and Problems
References

Reconfigurable Communication Infrastructure in the FCR
Introduction
Organization of the On-Chip Communication Infrastructure
Fine-Grained On-Chip Routing Elements in the FCR
Coarse-Grained On-Chip Routing Elements in the FCR
Fine-Grained On-Chip Configurable Input/Output Elements
Generic Organization of Input and Output Buffers for PCB Interface
Generic Organization of Output Buffers for Dynamic Links (Buses)
Reduction of Electromagnetic Noise and Crosstalk in Data Transfer Lines
Increasing Bandwidth Using DDR Transmission
Coarse-Grained Interface Elements for On-Board Communication
Summary
Exercises and Problems
References

System-Level Organization of the FCR
Introduction
FCR Organization Based on Static Links between PLD-Nodes
Organization of Dynamic System-Level Network in the Multi-PLD FCR
Organization of the Hybrid FCR with Programmable Processing Units
Organization of the Multiboard Communication Network
Summary
Exercises and Problems
References

Configuration Memory and Architecture Virtualization in RCS
Introduction
Generic Organization of Configuration Memory Hierarchy in the RCS
Concept of Virtualization of Hardware Resources in the RCS
Summary
Exercises and Problems
References

Reconfiguration Process Organization in the On-Chip Level of a Reconfigurable Computing System
Introduction
Reconfiguration of the On-Chip Resources in the RCS
Partitioning the On-Chip Field of Configurable Resources
Partitioning the On-Chip Configuration Memory for Partial Reconfiguration
Reconfiguration Process and Configuration Bit-File Structure
Configuration of Port and Bus Organization and Reconfiguration Time
Self-Reconfiguration of the On-Chip FCR and On-Chip Configuration Port
Organization of the On-Chip Configuration Cache Memory
Organization of the Internal Configuration Controller-Loader
Summary
Exercises and Problems
References

RCS Architecture Configuration and Runtime Reconfiguration
Introduction
Methods of Start-Up Configuration of the FCR at System Level
Serial Daisy-Chain Configuration Scheme
Serial and Parallel Ganged Configuration of Multiple PLDs
Parallel Daisy-Chain Configuration Scheme
Parallel Passive Configuration Scheme
Multibus Configuration Scheme for Multiple PLDs
Preconfiguration of Single or Multiple PLDs
Organization of Runtime Reconfiguration of the FCR at a System Level
Multiboot Runtime Self-Reconfiguration of Single and Multiple PLDs
Multiboot Runtime Reconfiguration with Distributed External Control
Multiboot Runtime Reconfiguration with Centralized External Control
Partial Runtime Reconfiguration with Centralized External Control
Partial Runtime Reconfiguration with Distributed Control
Summary
Exercises and Problems
References

Virtualization of the Architectural Components of a System on Chip
Introduction
General Organization of the Task Execution Process
Segmentation of a Task and Concept of Functional Segment
Segmentation according to Specification and Performance Requirements
Segmentation according to Mode-Switching Time and System Constrains
Implementation of Functional Segments in the Form of Virtual Components
Computation Acceleration Exploiting Different Sources of Parallelism
Computation Acceleration Using Pipelined Processing Circuits
Computation Acceleration Exploiting Control-Flow Parallelism
Computation Acceleration by Proper Resource Binding
Computation Acceleration Using Data Structure Segmentation
Organization of the Virtual Hardware Component
Summary
Exercises and Problems
References

Virtualization of Reconfigurable Computing System Architecture
Introduction
General Organization of the RCS Architecture
Concept of ASVP and Hardware Components Integration
ASVP with Statically Integrated Hardware Components
ASVP with Dynamically Integrated Software and Hardware Components
ASVP with Temporarily Integrated Hardware Components
ASVP with Spatially Integrated Hardware Components
Summary
Exercises and Problems
References

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