Switch-Level Timing Simulation of MOS VLSI Circuits / Edition 1

by Vasant B. Rao, David V. Overhauser, Timothy N. Trick, Ibrahim N. Hajj

Overview

Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In those days the programs were not user friendly, models were inadequate, and the algorithms were not very robust. The demand for simulation tools has been driven by the increasing complexity of integrated circuits and systems, and it has been aided by the rapid decrease in the cost of com­ puting that has occurred over the past several decades. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging. In this book only one aspect of the analysis and design process is examined. but it is a very important aspect that has received much attention over the years. It is the problem of accurate circuit and timing simulation.

Product Details

ISBN-13:	9780898383027
Publisher:	Springer US
Publication date:	11/30/1988
Series:	The Springer International Series in Engineering and Computer Science , #66
Edition description:	1989
Pages:	210
Product dimensions:	6.14(w) x 9.21(h) x 0.36(d)

Table of Contents

1. Introduction.- 2. Overview of Simulation Techniques.- 2.1 Analog vs Digital Simulation.- 2.2 Gate-Level Simulation.- 2.3 Switch-Level Logic Simulation.- 2.4 Mixed-Mode or Hybrid Simulation.- 2.5 Switch-Level Timing Simulation.- 3. Mos Network Partitioning and Ordering.- 3.1 MOS Network Components and Models.- 3.2 Partitioning the MOS Network into Blocks.- 3.3* Partitioning into Driver and Pass Transistors.- 3.4 Ordering of Partitioned Blocks.- 3.5 Conclusions.- 4. Switch-Level Timing Simulation.- 4.1 Overview.- 4.2 Waveform Representation.- 4.3 Simulation Algorithm.- 4.4 Deriving Inverter Voltage Equations.- 4.5 Determining the dc Output Voltage.- 4.6 Mapping Complex Blocks to Primitives.- 4.7 Parasitics.- 4.8 Sample Subcircuit Processing.- 5. Simulating Strongly Connected Components.- 5.1 Waveform Relaxation vs Time-point Relaxation.- 5.2 Dynamic Windowing.- 6. Performance of Idsim2.- References.- About The Authors.

Editorial Reviews

Based on two doctoral dissertations. Presents algorithms for the accurate estimation of analog waveforms in digital MOS circuits. Timing information obtained from these waveform estimates can be computed at least two orders of magnitude faster than by means of circuit simulation and the accuracy of the estimates is typically within 10% of the circuit simulation results. Annotation c. Book News, Inc., Portland, OR (booknews.com)

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