Pub. Date:
Springer US
Cache and Interconnect Architectures in Multiprocessors / Edition 1

Cache and Interconnect Architectures in Multiprocessors / Edition 1


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Product Details

ISBN-13: 9780792390749
Publisher: Springer US
Publication date: 07/31/1990
Edition description: 1990
Pages: 277
Product dimensions: 6.10(w) x 9.25(h) x 0.03(d)

Table of Contents

TLB Consistency and Virtual Caches.- The Cost of TLB Consistency.- Virtual-Address Caches in Multiprocessors.- Simulation and Performance Studies — Cache Coherence.- A Critique of Trace-Driven Simulation for Shared-Memory Multiprocessors.- Performance of Symmetry Multiprocessor System.- Analysis of Cache Invalidation Patterns in Shared-Memory Multiprocessors.- Memory-Access Penalties in Write-Invalidate Cache Coherence Protocols.- Performance of Parallel Loops using Alternate Cache Consistency Protocols on a Non-Bus Multiprocessor.- Predicting the Performance of Shared Multiprocessor Caches.- Cache Coherence Protocols.- The Cache Coherence Protocol of the Data Diffusion Machine.- SCI (Scalable Coherent Interface) Cache Coherence.- Interconnect Architectures.- Performance Evaluation of Wide Shared Bus Multiprocessors.- Crossbar-Multi-processor Architecture.- “CHESS” Multiprocessor—A Processor-Memory Grid for Parallel Programming.- Software Cache Coherence Schemes.- Software-directed Cache Management in Multiprocessors.

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