Cache and Interconnect Architectures in Multiprocessors / Edition 1

by Michel Dubois, Shreekant S. Thakkar

Overview

Cache And Interconnect Architectures In Multiprocessors Eilat, Israel May 25-261989 Michel Dubois UniversityofSouthernCalifornia Shreekant S. Thakkar SequentComputerSystems The aim of the workshop was to bring together researchers working on cache coherence prools for shared-memory multiprocessors with various interconnect architectures. Shared-memory multiprocessors have become viable systems for many applications. Bus­ based shared-memory systems (Eg. Sequent's Symmetry, Encore's Multimax) are currently limited to 32 processors. The fIrst goal of the workshop was to learn about the performance ofapplications on current cache-based systems. The second goal was to learn about new network architectures and prools for future scalable systems. These prools and interconnects would allow shared-memory architectures to scale beyond current imitations. The workshop had 20 speakers who talked about their current research. The discussions were lively and cordial enough to keep the participants away from the wonderful sand and sun for two days. The participants got to know each other well and were able to share their thoughts in an informal manner. The workshop was organized into several sessions. The summary of each session is described below. This book presents revisions of some of the papers presented at the workshop.

Product Details

ISBN-13:	9780792390749
Publisher:	Springer US
Publication date:	07/31/1990
Edition description:	1990
Pages:	277
Product dimensions:	6.10(w) x 9.25(h) x 0.03(d)

Table of Contents

TLB Consistency and Virtual Caches.- The Cost of TLB Consistency.- Virtual-Address Caches in Multiprocessors.- Simulation and Performance Studies — Cache Coherence.- A Critique of Trace-Driven Simulation for Shared-Memory Multiprocessors.- Performance of Symmetry Multiprocessor System.- Analysis of Cache Invalidation Patterns in Shared-Memory Multiprocessors.- Memory-Access Penalties in Write-Invalidate Cache Coherence Prools.- Performance of Parallel Loops using Alternate Cache Consistency Prools on a Non-Bus Multiprocessor.- Predicting the Performance of Shared Multiprocessor Caches.- Cache Coherence Prools.- The Cache Coherence Prool of the Data Diffusion Machine.- SCI (Scalable Coherent Interface) Cache Coherence.- Interconnect Architectures.- Performance Evaluation of Wide Shared Bus Multiprocessors.- Crossbar-Multi-processor Architecture.- “CHESS” Multiprocessor—A Processor-Memory Grid for Parallel Programming.- Software Cache Coherence Schemes.- Software-directed Cache Management in Multiprocessors.

Editorial Reviews

A collection of invited papers concerning cache coherence protocols for general interconnects. Covers the major efforts now under way to understand the architecture and performance issues of cache-based multiprocessor computer systems. Annotation c. Book News, Inc., Portland, OR (booknews.com)

Booknews