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1: The Method of Logical Effort
Designing a circuit to achieve the greatest speed or to meet a delay constraint presents a bewildering array of choices. Which of several circuits that produce the same logic function will be fastest? How large should a logic gate's transistors be to achieve least delay? And how many stages of logic should be used to obtain least delay? Sometimes, adding stages to a path reduces its delay!
The method of logical effort is an easy way to estimate delay in a cmos circuit. We can select the fastest candidate by comparing delay estimates of different logic structures. The method also specifies the proper number of logic stages on a path and the best transistor sizes for the logic gates. Because the method is easy to use, it is ideal for evaluating alternatives in the early stages of a design and provides a good starting point for more intricate optimizations.
This chapter describes the method of logical effort and applies it to simple examples. Chapter 2 explores more complex examples. These two chapters together provide all you need to know to apply the method of logical effort to a wide class of circuits. We devote the remainder of this book to derivations that show why the method of logical effort works, to some detailed optimization techniques, and to the analysis of special circuits such as domino logic and multiplexers.
1.1 Introduction
To set the context of the problems addressed by logical effort, we begin by reviewing a simple integrated circuit design flow. We will see that topology selection and gate sizing are key steps of the flow. Without a systematic approach, these steps are extremely tedious and time-consuming. Logical effort offers such an approach to these problems.
Figure 1.1 shows a simplified chip design flow illustrating the logic, circuit, and physical design stages. The design starts with a specification, typically in textual form, defining the functionality and performance targets of the chip. Most chips are partitioned into more manageable blocks so that they may be divided among multiple designers and analyzed in pieces by CAD tools. Logic designers write register transfer level (RTL) descriptions of each block in a language like Verilog or VHDL and simulate these models until they are convinced the specification is correct. Based on the complexity of the RTL descriptions, the designers estimate the size of each block and create a floorplan showing relative placement of the blocks. The floorplan allows wire-length estimates and provides goals for the physical design.
Given the RTL and floorplan, circuit design may begin. There are two general styles of circuit design: custom and automatic. Custom design trades additional human labor for better performance. In a custom methodology, the circuit designer has flexibility to create cells at a transistor level or choose from a library of predefined cells. The designer must make many decisions: Should I use static cmos, transmission gate logic, domino circuits, or other circuit families? What circuit topology best implements the functions specified in the RTL? Should I use NAND, NOR, or complex gates? After selecting a topology and drawing the schematics, the designer must choose the size of transistors in each logic gate. A larger gate drives its load more quickly, but presents greater input capacitance to the previous stage and consumes more area and power. When the schematics are complete, functional verification checks that the schematics correctly implement the RTL specification. Finally, timing verification checks that the circuits meet the performance targets. If performance is inadequate, the circuit designer may try to resize gates for improved speed, or may have to change the topology entirely, exploiting parallelism to build faster structures at the expense of more area or switching from static cmos to faster domino gates.
Automatic circuit design uses synthesis tools to choose circuit topologies and gate sizes. Synthesis takes much less time than manually optimizing paths and drawing schematics, but is generally restricted to a fixed library of static cmos cells and produces slower circuits than those designed by a skilled engineer. Advances in synthesis and manufacturing technology continue to expand the set of problems that synthesis can acceptably solve, but for the foreseeable future, high-end designs will require at least some custom circuits. Synthesized circuits are normally logically correct by construction, but timing verification is still necessary. If performance is inadequate, the circuit designer may set directives for the synthesis tool to improve critical paths.
When circuit design is complete, layout may begin. Layout may also be custom or may use automatic place and route tools. Design rule checkers (DRC) and layout versus schematic (LUS) checks are used to verify the layout. Postlayout timing verification ensures the design still meets timing goals after including more accurate capacitance and resistance data extracted from the layout; if the estimates used in circuit design were inaccurate, the circuits may have to be modified again. Finally, the chip is "taped out" and sent for manufacturing.
One of the greatest challenges in this design flow is meeting the timing specifications, a problem known as timing convergence. If speed were not a concern, circuit design would be much easier, but if speed were not a concern, the problem could be solved more cost-effectively in software.
Even experienced custom circuit designers often expend a tremendous amount of frustrating effort to meet timing specifications. Without a systematic approach, most of us fall into the "simulate and tweak" trap of making changes in a circuit, throwing it into the simulator, looking at the result, making more changes, and repeating. Because circuit blocks often take half an hour or more in simulation, this process is very time-consuming. Moreover, the designer often tries to speed up a slow gate by increasing its size. This can be counterproductive if the larger gate now imposes greater load on the previous stage, slowing the previous stage more than improving its own delay! Another problem is that without an easy way of estimating delays, the designer who wishes to compare two topologies must draw, size, and simulate a schematic of each. This process takes a great deal of time and discourages such comparisons. The designer soon realizes that a more efficient and systematic approach is needed and over the years develops a personal set of heuristics and mental models to assist with topology selection and sizing.
Users of synthesis tools experience similar frustrations with timing convergence, especially when the specification is near the upper limit of the tool's capability. The synthesis equivalent of "simulate and tweak" is "add constraints and resynthesize"; as constraints fix one timing violation, they often introduce a new violation on another path. Unless the designer looks closely at the output of the synthesis and understands the root cause of the slow paths, adding constraints and resynthesizing may never converge on an acceptable result...
