Table of Contents
Preface.
1 Introduction.
1.1 Power Supply Noise.
1.2 Power Network Modeling.
1.3 Modelling of Switching Currents.
1.4 On-Chip Decoupling Capacitance.
1.5 On-Chip Inductance.
1.6 Process Scaling Impacts.
1.7 Summary.
2 Design Perspectives.
2.1 Planning for Communication Chips.
2.2 Planning for Microprocessor Chips.
2.3 IBM CAD Methodology.
2.4 Design for IR Drop.
2.5 Package-Level Methodology.
2.6 Summary.
3 Electromigration.
3.1 Basic Definitions and EM Rules.
3.2 EM Analysis Tool.
3.3 Full-Chip EM Methodology.
3.4 Summary.
4 IR Voltage Drop.
4.1 Causes of IR Drop.
4.2 Overview of IR Analysis.
4.3 Static Analysis Approach.
4.4 Dynamic Analysis Approach.
4.5 Circuit Analysis with IR Drop Impacts.
4.6 Summary.
5 Power Grid Analysis.
5.1 Introduction.
5.2 Executing the Tool.
5.3 Advanced Static Analysis.
5.4 Dynamic Analysis.
5.5 Layout Exploration.
5.6 Summary.
6 Microprocessor Design Examples.
6.1 Intel IA-32 Pentium-III.
6.2 Sun UltraSPARC.
6.3 Hitachi SuperH Microprocessor.
6.4 IBM S/390 Microprocessor.
6.5 Sun SPARC 64b Microprocessor.
6.6 Intel IA-64 Microprocessor.
6.7 Summary.
7 Package and I/O Design for Power Delivery.
7.1 Flip-Chip Package.
7.2 Simultaneous Switching Noise (SSN).
7.3 Case Study of a Microprocessor-Like Chip.
7.4 Power Supply Measurement.
7.5 I/O Pads for Power/Ground Supplies.
Glossary.
References.
Index.
